1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having storage capacitors.
2. Description of the Background Art
A storage capacitor in a semiconductor storage device must be adapted to data holding of one second or more and read/write cycle of 100 MHz or more, so it is required to allow a wide dynamic range from under 1 Hz to over 100 MHz.
Now, the silicon oxide and silicon nitride films which have been conventionally used as dielectric materials of capacitors are amorphous materials, so that it has been relatively easy to ensure the dynamic range when capacitors are made using these materials. This is because control of in-film defects is relatively easy.
However, the recent reduction in size and increase in integration degree of semiconductor devices are now making it difficult to obtain sufficient electrostatic capacitance using these materials having lower dielectric constants, so that the tendency now is turning toward use of polycrystalline dielectrics having higher dielectric constants, such as ditantalum pentaoxide (Ta2O5) and BST (barium strontium titanate). Ta2O5 is usually used in polycrystalline form to obtain higher dielectric constant, though it may be used also in amorphous form.
However, polycrystalline materials generally suffer larger dielectric loss because of the interfacial polarization or orientation polarization due to grain boundary, interface conditions, etc., which applies also to Ta2O5, BST and the like.
The dielectric loss resulting from the interfacial polarization and orientation polarization will now be described referring to FIGS. 11 and 12.
FIG. 11 shows an equivalent circuit representing a real capacitor using ideal capacitor and ideal resistor. The ideal capacitor is a capacitor in which resistance and inductance of electrodes and interconnection can be neglected, there is no capacitance variation resulting from the effects of applied voltage, temperature, humidity, pressure, etc., and the time required for polarization is infinitely close to zero; it is thus a capacitor with less capacitance variation due to frequency and no leakage current, for example.
The ideal resistor is a resistor whose characteristics are free from parasitic inductance and variations in resistance value resulting from effects of applied voltage, temperature, humidity, pressure, etc.
However, the leakage current, resistance of electrodes and interconnection, time required for polarization etc. cannot be neglected with a real capacitor; FIG. 11 shows the leakage current component as the resistor R0 parallel-connected to the ideal capacitor C0 and the resistance of electrodes and interconnection as the resistor R10 series-connected to the ideal capacitor C0.
Polarization occurs as positive and negative charges transfer when an electric field is applied to electrodes of the capacitor, which includes the four mechanisms: electronic polarization due to displacement of electron cloud, ionic polarization due to displacement of ions, orientation polarization due to rotation of the dipole moment of molecules, and interfacial polarization caused as charges in the dielectric transfer and are accumulated at the interface. Development of polarization by these mechanisms takes a certain time and a time delay therefore occurs with respect to the phase of the electric field.
The electronic polarization and ionic polarization occur when an electric field having a frequency in the ultraviolet or microwave region is applied, so that the orientation polarization and interfacial polarization must be considered in common semiconductor devices which operate at lower frequencies.
FIG. 11 also shows them as the equivalent circuit. That is to say, the polarization components are represented as the series circuits D1, D2, D3 and D4 formed of the capacitor C1 and resistor R1, the capacitor C2 and resistor R2, the capacitor C3 and resistor R3, and the capacitor C4 and resistor R4 which are connected to the ideal capacitor C0 in parallel.
A product of the capacitor component C (unit F: Farad) and the resistance component R (unit xcexa9: Ohm) of each circuit corresponds to the relaxation time xcfx84 which is used as an indication of the time required for polarization. Accordingly, when the capacitance values of the capacitors C1 to C4 are taken as C1 to C4 and the resistance values of the resistors R1 to R4 are taken as R1 to R4, then the relaxation times xcfx841 to xcfx844 of the series circuits D1 to D4 are given as C1R1, C2R2, C3R3 and C4R4, respectively.
Generally, while a polarization component functions as capacitor with respect to electric fields having frequencies lower than the reciprocal of the relaxation time, the polarization component cannot follow in operation as capacitor with respect to electric fields having frequencies higher than the reciprocal of the relaxation time, and then the polarization component cannot contribute as capacitance.
Study on the frequency characteristic of the capacitor capacitance shows a trend that the capacitance becomes smaller at higher frequencies, which is due to the fact that the polarization components cannot follow at high frequencies and therefore cannot contribute as capacitance. It is assumed in FIG. 11 that four polarization components having different relaxation times exist and they are shown as the series circuits D1 to D4.
In this example, the relaxation times xcfx841 to xcfx844 are assumed to become larger in the order of the relaxation time xcfx841, which is the shortest, and then xcfx842, xcfx843, and xcfx844.
A real capacitor having such configuration exhibits a frequency characteristic as shown in FIG. 12.
That is to say, when the frequency is represented as the reciprocal of the relaxation time, and if the frequency is lower than 1/xcfx844, all of the capacitors C1 to C4 as polarization components can follow in polarization, so that the capacitance of the real capacitor is the sum total of the ideal capacitor C0 and the capacitors C1 to C4.
However, when the frequency becomes equal to or higher than 1/xcfx844, then the capacitor C4 cannot follow, and the capacitance of the real capacitor is the sum total of the ideal capacitor C0 and the capacitors C1 to C3.
Similarly, when the frequency becomes equal to or higher than 1/xcfx843, the capacitor C3 cannot follow, and when the frequency becomes equal to or higher than 1/xcfx842, the capacitor C2 cannot follow, and when the frequency becomes equal to or higher than 1/xcfx841, the capacitor C1 cannot follow, and finally, all of the polarization components cannot contribute as capacitance and only the capacitance of the ideal capacitor C0 remains.
Actually, the relaxation times of the polarization components continuously exist and the frequency characteristic also vary continuously.
A storage capacitor in a semiconductor storage device can be represented similarly as a plurality of capacitors in which polarization components are connected in parallel; FIGS. 13 to 15 show a problem of the storage capacitor which is caused by dielectric loss resulting from interfacial polarization and orientation polarization.
In FIGS. 13 to 15, the storage capacitor CP which is subjected to writing and reading of data is shown as a capacitor having, in addition to the ideal capacitor C0, the series circuits D1 to Dn as polarization components, which are formed of n capacitors C1 to Cn and resistors R1 to Rn series-connected respectively to the capacitors C1 to Cn.
As stated above, the capacitors C1 to Cn have different relaxation times xcfx841 to xcfx84n, where xcfx841 is the shortest and xcfx84n is the longest.
FIG. 13 shows a condition of the storage capacitor thus constructed, where data is written in for the first time.
In FIG. 13, charge is stored in the ideal capacitor C0; when the frequency of the applied voltage for writing is higher than 1/xcfx841, the capacitors C1 to Cn cannot follow in the operation of storing charge and they cannot contribute to the storage of charge. Series circuits which cannot follow are shown by broken lines.
Accordingly, as shown by the equation (1) below, the amount of charge, QA, of the storage capacitor CP is given as a product of the capacitance C0 of the ideal capacitor C0 and the voltage V0 applied to the electrodes of the storage capacitor CP.
QA=C0xc2x7V0 . . . xe2x80x83xe2x80x83(1)
However, when the data is held as shown in FIG. 14, the capacitors C1 to Cn, which could not follow when data is written, receive charge from the ideal capacitor C0 and sequentially store charge in accordance with their respective relaxation times. Series circuits which cannot store charge are shown by broken lines.
As a result, as shown by the equation (2) below, the voltage V of the electrodes of the storage capacitor CP is given as the voltage V0 divided by the capacitance including the polarization components.
V=V0/(C0+C1+C2+. . . )xe2x80x83xe2x80x83(2)
In this condition, when data is read as shown in FIG. 15, the capacitors C1 to Cn cannot follow the reading of charge if the frequency of the applied voltage for reading is higher than 1/xcfx841, and then only the charge remaining in the ideal capacitor C0 is read, resulting in partial loss of the stored charge.
In the equation (3) below, the read charge QB is given as a product of the capacitance C0 of the ideal capacitor C0 and the voltage V of the electrodes of the storage capacitor CP.                                                                         Q                B                            =                              xe2x80x83                            ⁢                                                C                  0                                ·                V                                                                                        =                              xe2x80x83                            ⁢                              (                                  1                  -                                                                                                              C                          1                                                +                                                                              C                            2                                                    ⁢                                                      xe2x80x83                                                    ⁢                          …                                                                                                                      C                          0                                                +                                                  C                          1                                                +                                                                              C                            2                                                    ⁢                                                      xe2x80x83                                                    ⁢                          …                                                                                      ·                                          Q                      A                                                                      )                                                                        (        3        )            
In this way, the charge of the ideal capacitor C0 transfers to the capacitors C1 to Cn and as a result the charge of the storage capacitor CP is dissipated. In a BST capacitor formed by a conventional method, the amount of charge lost due to such behavior may reach a maximum of 20% of the amount of stored charge. This causes problems in the memory operation and therefore the dielectric loss should be reduced as well as the leakage current.
Now a conventional method for manufacturing a storage capacitor is briefly explained. After formation of the capacitor portion, an oxygen annealing process is performed for about 20 minutes at 300 to 500xc2x0 C. in order to repair damage produced during formation of the capacitor electrodes.
Such a process for repairing damage is necessary if a polycrystalline material formed of metal oxide, such as BST and PZT (lead zirconate titanate), is used as the capacitor dielectric. Omitting the oxygen annealing will result in problems such as an increase in leakage current, reduction in breakdown voltage, etc. When Ta2O5 is used as the dielectric, for example, ozone annealing is effective as well as the oxygen annealing.
However, when the breakdown voltage is recovered by such oxygen annealing, the leakage current characteristic is such as shown in FIG. 16.
In FIG. 16, the horizontal axis shows the applied voltage to the electrodes in terms of electric field strength (kV/cm) and the vertical axis shows the leakage current density, where a current component having small electric field dependence is seen in the relatively low electric field range of 500 kV/cm or lower.
This current component depends on the voltage application time; the current value I is often represented, with respect to the voltage application time t, as I=Axc2x7t(xe2x88x92xcex1) (xcex1, A are constants), which is called absorption current.
The integral amount of the absorption current corresponds to the amount of dissipated charge in the stored charge in the storage capacitor, whose value must be reduced to ⅕ to {fraction (1/10)} to enable stable operation of the semiconductor device.
Actually, for a reason in measurement, what is measured is not the absorption current, but measurements of dielectric loss tangent (tan xcex4) with an LCR meter are used as indication, where its allowable range has conventionally been tan xcex4=0.01 to 0.03.
A first aspect of the present invention is directed to a method for manufacturing a semiconductor device which comprises an underlying layer and a plurality of capacitors formed on said underlying layer, each of said plurality of capacitors having a lower electrode, a polycrystalline dielectric film, and an upper electrode provided in opposed relation to the lower electrode with the polycrystalline dielectric film interposed therebetween. According to the present invention, the method comprises the steps of: (a) forming the lower electrodes, the polycrystalline dielectric films, and the upper electrodes in order on the underlying layer to form the capacitors; (b) after formation of the upper electrodes, applying a rapid thermal annealing to at least the plurality of capacitors; and (c) after the rapid thermal annealing, performing an annealing in an oxidative gas.
Preferably, according to a second aspect, the semiconductor device manufacturing method further comprises, between the step (b) and the step (c), a step (d) of exposing at least the plurality of capacitors to a plasma comprising an oxidative gas.
Preferably, according to a third aspect, in the semiconductor device manufacturing method, the step (b) comprises a step of heating at 500 to 800xc2x0 C. for 3 to 60 seconds.
Preferably, according to a fourth aspect, in the semiconductor device manufacturing method, the oxidative gas comprises at least one of an oxygen gas and a gas composed of molecules including oxygen atoms, and the step (c) comprises a step of heating at 300 to 550xc2x0 C. for 30 minutes to 6 hours in the oxidative gas.
Preferably, according to a fifth aspect, in the semiconductor device manufacturing method, the step (a) comprises a step of forming at least the lower electrodes or the upper electrodes with one element in the platinum group elements or an alloy comprising at least one element in the platinum group elements.
Preferably, according to a sixth aspect, in the semiconductor device manufacturing method, the step (d) comprises a step of heating at least the plurality of capacitors at 300 to 500xc2x0 C.
Preferably, according to a seventh aspect, the semiconductor device manufacturing method further comprises, between the step (b) and the step (c), a step (d) of applying ultraviolet radiation to an oxidative gas to activate oxygen and exposing at least the plurality of capacitors to the activated oxygen.
Preferably, according to an eighth aspect, the semiconductor device manufacturing method further comprises, between the step (b) and the step (c), a step (d) of exposing at least the plurality of capacitors to a plasma which comprises fluorine or chlorine.
Preferably, according to a ninth aspect, the semiconductor device manufacturing method further comprises, between the step (b) and the step (c), a step (d) of heating at least the plurality of capacitors to 300 to 550xc2x0 C. and exposing at least the plurality of capacitors in a gas composed of molecules including fluorine atoms for 30 minutes to 6 hours.
According to the semiconductor device manufacturing method of the first aspect of the invention, a rapid thermal annealing is performed after formation of the capacitors. Oxygen contained in the lower and upper electrodes then leaves and the leaving oxygen is supplied to the interface of the polycrystalline dielectric film and repair crystal defects, thus reducing the dielectric loss of the polycrystalline dielectric film. Further, causing oxygen contained in the lower and upper electrodes to leave also reduces the resistivity of the lower and upper electrodes. Further, an annealing is performed in an oxidative gas after the rapid thermal annealing, which recovers the capacitor breakdown voltage reduced by the rapid thermal annealing.
According to the semiconductor device manufacturing method of the second aspect of the invention, after the rapid thermal annealing and before the annealing in an oxidative gas, at least the plurality of capacitors are exposed to a plasma which contains oxygen, which further reduces the dielectric loss of the polycrystalline dielectric film.
According to the semiconductor device manufacturing method of the third aspect of the invention, the dielectric loss of the polycrystalline dielectric film can be effectively reduced.
According to the semiconductor device manufacturing method of the fourth aspect of the invention, the reduced breakdown voltage of the capacitors can be effectively recovered.
According to the semiconductor device manufacturing method of the fifth aspect of the invention, at least one of the lower and upper electrodes is formed of an element in the platinum group elements or an alloy containing at least one element in the platinum group elements. Such materials do not have strong reducing property, so that the polycrystalline dielectric film is not reduced even if it is made of an easily reduced oxide. Accordingly the insulating property is maintained and the function as a capacitor is not deteriorated.
According to the semiconductor device manufacturing method of the sixth aspect of the invention, the dielectric loss of the polycrystalline dielectric film can be effectively reduced.
According to the semiconductor device manufacturing method of the seventh aspect of the invention, after the rapid thermal annealing and before the annealing in an oxidative gas, ultraviolet radiation is applied to an oxygen-containing gas to activate oxygen and at least the plurality of capacitors are exposed to the activated oxygen. Thus the dielectric loss of the polycrystalline dielectric film can be further reduced without causing charge-up.
According to the semiconductor device manufacturing method of the eighth aspect of the invention, after the rapid thermal annealing and before the annealing in an oxidative gas, the plurality of capacitors are exposed to a plasma which contains fluorine or chlorine, which further reduces the dielectric loss of the polycrystalline dielectric film.
According to the semiconductor device manufacturing method of the ninth aspect of the invention, after the rapid thermal annealing and before the annealing in an oxidative gas, the plurality of capacitors are heated to 300 to 550xc2x0 C. and exposed in a gas formed of molecules including fluorine atoms for 30 minutes to 6 hours, thus further reducing the dielectric loss of the polycrystalline dielectric film.
The present invention has been made to solve the problem described above, and an object of the present invention is to provide a semiconductor device manufacturing method in which the value of the dielectric loss tangent of the dielectric film forming storage capacitors is reduced to prevent dielectric loss of the stored charge of the storage capacitors.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.